1. Field of the Invention
The present invention generally relates to a nonvolatile ferroelectric memory device, and more specifically, to a technology of improving speed of read/write operations depending on a process of serial data of a nonvolatile ferroelectric memory device having a multi-bit serial cell structure.
2. Description of the Related Art
In general, circuits having various functions are positioned together in a chip having a small area as a system structure has been complicated and developed to have high performance. However, the number of buses for transmitting data increases, which results in degradation of high integration. As a result, a method for transmitting serial data using a serial bus is applied.
FIG. 1 is a diagram illustrating a conventional nonvolatile ferroelectric memory device.
The conventional nonvolatile ferroelectric memory device comprises a 4-bit serial cell 1 and a switching transistor T5. Here, the serial cell 1, which is connected serially between a bit line BL and the switching transistor T5, comprises a plurality of NMOS transistors T1˜T4 whose switching operations are controlled by each of word lines WL1˜WL4.
The plurality of ferroelectric capacitors FC1˜FC4 are connected in parallel between the word lines WL1˜WL4 and nodes N1˜N4, respectively. Also, the switching transistor T5, which is connected between the serial cell 1 and the bit line BL, has a gate to receive a write enable control signal WEC.
The serial cell 1 comprises a plurality of unit cells C which share one bit line BL. As a result, the write enable control signal WEC is activated in a write or restore operation, so that write data are written sequentially in four unit cells C.
Referring to FIGS. 2 and 3, the operation of the above-described conventional nonvolatile ferroelectric memory device is explained.
At a read mode, the four unit cells are sequentially accessed to store sensed data sequentially in a register 2. On the other hand, at a write (restore) mode, the data stored in the register 2 are sequentially restored in each unit cell C.
More specifically, in a period t1, when the word line WL1 is activated at the read mode, the NMOS transistor T1 is turned on. Then, a sense amplifier senses cell data applied through the bit line BL, and stores first cell data D1 in the register 2.
Thereafter, in a period t2, when the word line WL2 is activated, the NMOS transistor T2 is turned on. Then, the sense amplifier senses the cell data applied through the bit line BL, and stores second cell data D2 in the register 2. Here, the word line WL1 is continuously kept at an active state, so that the cell data stored in the ferroelectric capacitor FC2 are transmitted to the bit line BL.
Thereafter, in a period t3, when the word line WL3 is activated, the NMOS transistor T3 is turned on. Then, the sense amplifier senses cell data applied through the bit line BL, and stores third cell data D3 in the register 2. Here, the word lines WL1 and WL2 are continuously kept at an active state, so that the cell data stored in the ferroelectric capacitor FC3 are transmitted to the bit line BL.
Next, in a period t4, when the word line WL4 is activated, the NMOS transistor T4 is turned on. Then, the sense amplifier senses the cell data applied through the bit line BL, and stores fourth cell data D4 in the register 2. Here, the word lines WL1˜WL3 are continuously kept at an active state, so that the cell data stored in the ferroelectric capacitor FC4 are transmitted to the bit line BL.
Here, a restore operation is not performed at the read mode in the periods t1˜t4. After the final cell data D4 is read in the period t4, the first cell data D1 is restored in the cell C from a period t5.
That is, at a write (restore) mode, when the write enable control signal WEC is activated, the switching transistor T5 is turned on.
Then, in the period t5, the first cell data D1 stored in the register 2 is stored in the ferroelectric capacitor FC1 through the bit line BL. Thereafter, when the word line WL1 transits from ‘high’ to ‘low’, high data are written in the ferroelectric capacitor FC1. Here, the word lines WL2˜WL4 are continuously kept at the active state, so that the cell data D1 is transmitted to a node ND1.
Thereafter, in a period t6, the second cell data D2 stored in the register 2 is stored in the ferroelectric capacitor FC2 through the bit line BL. Then, the word line WL2 transits from ‘high’ to ‘low’, high data are written in the ferroelectric capacitor FC2. Here, the word lines WL3˜WL4 are continuously kept at the active state, so that the cell data D2 is transmitted to a node ND2.
Next, in a period t7, the third cell data D3 stored in the register 2 is stored in the ferroelectric capacitor FC3 through the bit line BL. Then, the word line WL3 transmits from ‘high’ to ‘low’, high data are written in the ferroelectric capacitor FC3. Here, the word line WL4 is continuously kept at the active state, so that the cell data D3 is transmitted to a node ND3.
Then, in a period t8, the fourth cell data D4 stored in the register 2 is stored in the ferroelectric capacitor FC4 through the bit line BL. Thereafter, the word line WL4 transits from ‘high’ to ‘low’, high data are written in the ferroelectric capacitor FC4.
However, in the conventional nonvolatile ferroelectric memory device, the read operation is required after the write operation of the four cell data D1˜D4 is performed. In other words, other cells cannot be accessed while the write operation is performed on the four cell data D1˜D4.
As a result, since the conventional nonvolatile ferroelectric memory device requires an additional restore time after the sensing operation of the cell data, the data transmission speed is degraded in transmission of the successive serial data.